Designers Corner with Prof. Mike Smith  Part 1  Part 2

Getting organized

Hamish worked on the digital part of the design and completed a draft schematic for the interface between Xilinx FPGA, CPLD, the ROM and SRAM. Mike worked on the analog (the PHY) interface including the magnetics necessary to couple the PHY to the twisted-wire cable. We chose the Level One PHY chip because of the fairly detailed references designs (and partly because Dave Van den had also chosen this part for his board). The reference designs helped considerably when it came to the analog part of the board layout. We realized careful layout was important for 100Mbps operation. Brandon, our new intern, began work on the parallel port.

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